1. Field of the Invention
This invention relates to semiconductor processing and, more particularly, to a method for preventing damage to an alignment mark from chemical-mechanical polishing and to an alignment mark having a substantially reduced chance of being damaged by such polishing.
2. Description of the Related Art
Semiconductor processing, and particularly integrated circuit fabrication, involves the formation of numerous structures or features upon a semiconductor topography. The base of the semiconductor topography is typically a wafer of single crystal silicon. The features are placed in localized areas of the semiconductor topography and are conductive, non-conductive, or semi-conductive (i.e. rendered conductive in defined areas with dopants). As the features are usually only a few microns or less in size, their precise placement upon the semiconductor topography can have a large effect upon the functionality of the finished product. The surface dimensions of the features may be defined by a process known as photolithography ("lithography").
In lithography, radiation is used to pattern a photosensitive film (i.e. resist) deposited upon the semiconductor topography. Patterning of the resist generally involves first selectively exposing the resist to radiation through an exposure mask. Ultraviolet light is the primary form of radiation used to pattern resists, but x-rays and electron beams are growing in popularity. The exposure mask may be either a full mask carrying the entire pattern to be transferred to the wafer or a reticle carrying only a portion of the entire pattern. Because of the difficulty of making a mask capable of projecting a quality image over an entire wafer at once, reticles are more common than full masks. Reticles are used to step-and-repeat an image across a wafer, and exposure tools that operate in such a fashion are called steppers.
The passage of radiation through the exposure mask is partially inhibited by a patterned coating formed on the mask. The patterned coating is often made of chrome. The shape of the patterned coating corresponds to the desired pattern to be transferred to the resist. Because the patterned coating blocks the passage of radiation where the coating is present, the use of an exposure mask having such a coating allows a particular pattern within the resist to be selectively exposed to radiation.
Two properties of resists make them extremely useful in lithographic processes. First, the solubility of resists in particular chemical solvents (developers) may be altered by exposure to appropriate radiation. Second, a resist layer may be hardened to become resistant to attack by an etchant capable of selectively removing exposed layers underneath. Resists are classified as either negative or positive based upon their reaction to radiation exposure. Negative resists are relatively soluble as deposited, but become insoluble upon exposure to radiation. Positive resists are relatively insoluble as deposited, but solubilize upon exposure to radiation. Regardless of the type of radiation used, after selective exposure to radiation as described above some portions of the resist layer are insoluble and other portions are soluble. The resist layer is then washed with a developer configured to remove the relatively soluble portions of the resist while leaving as much as possible of the relatively insoluble portions of the resist. Removal of the insoluble portions transfers the exposure mask pattern to the resist. With the resist patterned, an etchant may be used to remove underlying portions of the semiconductor topography unprotected (i.e., not covered) by the resist. The resist is then removed, making the transfer of the exposure mask pattern complete.
During photolithography, the exposure mask pattern must be properly positioned relative to previously formed patterns upon the semiconductor topography. One measure of how closely different levels of a pattern are aligned is termed registration. Proper registration, or alignment, is essential if a functioning circuit is desired. Alignment of the exposure mask pattern to previously formed layers is often accomplished using a structure called an alignment mark. An alignment mark typically contains a plurality of patterns formed within an alignment mark area of the wafer and having a particular spatial relationship. Alignment marks are usually formed in the edge area of the wafer or near the scribe lines separating die on the wafer.
Modern steppers almost universally use automatic alignment systems to align the reticle to the wafer. The reticle typically contains alignment marks that correspond or are complementary in shape to the alignment marks formed on the wafer, but are of dissimilar size. In a conventional alignment system, low energy laser beams are passed through the alignment marks on the reticle and reflected off the corresponding alignment marks on the wafer. The reflected signal is analyzed, and the chuck on which the wafer is placed is repositioned. The process may be continued until the marks are aligned.
FIG. 1 presents a cross-sectional view of silicon wafer 100 having a conventional alignment mark formed therein. The alignment mark includes grooves 102 formed in alignment mark area 104 of wafer 100. A stepper attempting to align to the mark shown in FIG. 1 can analyze radiation reflected off wafer 100 to determine the relative position along points of the wafer surface. A typical grating alignment system used by steppers reads the elevation drop and rise that occurs as the laser scans from the original upper surface of wafer 100 next to grooves 102 to the recessed upper surface of wafer 100 within grooves 102 and then back up to the original upper surface of wafer 100. These readings may then be compared to predicted results to determine the position of the reticle relative to the wafer. The accuracy of the alignment process is often highly dependent on the alignment mark having sharply defined transitions from the surface of wafer 100 to the bottom of grooves 102. The surface of wafer 100 should preferably be kept uniformly flat and the walls of groove 102 should preferably be substantially vertical to allow the alignment system to receive the clearest signal.
Unfortunately, subsequent integrated circuit processing steps can result in damage to the wafer surface within the alignment mark area and destruction of the sharp transitions that may be essential for optimal alignment. As shown in FIG. 2, subsequent processing steps necessary for the fabrication of features upon wafer 100 may result in the deposition of layers such as silicon dioxide ("oxide") layer 106, silicon nitride ("nitride") layer 108, and CMP oxide layer 110 upon wafer 100. These layers are then typically planarized to the surface of wafer 100 using chemical-mechanical polishing ("CMP"). The upper surface of the semiconductor substrate next to and within alignment mark area 104 is often directly polished during this step. Any remaining portions of the above-described oxide and nitride layers are usually removed in further processing. Oxide fill material 112 may then be deposited over wafer 100, filling grooves 102. The oxide fill material is then polished such that it is substantially contained within grooves 102 and such that its upper surfaces are relatively coplanar with the upper surface of wafer 100 (see FIG. 3). Because of the desire for a high degree of planarization, the upper surface of wafer 100 may again be exposed to direct polishing for a substantial period. As can be seen in this example, conventional semiconductor fabrication processes often result in the polishing of the surface of wafer 100 in and near alignment mark area 104 for a substantial period of time.
Direct polishing of the surface of wafer 100 in alignment mark area 104 can do a great deal of damage to the silicon surface of wafer 100, mostly due to the conformability of the CMP pad and/or mechanical or chemical abrasiveness of the CMP slurry. As shown in FIG. 3, polishing can result in distortion of the surface of wafer 100 in and near alignment mark area 104. Distortion of the wafer upper surface can result in the wafer surface being elevationally displaced from desired levels. For example, the CMP pad may bend into materials such as oxide fill material 112 during the polishing process. Such uneven pad application can result in an upper corner of groove 102 being polished down, destroying the sharp transition between the wafer upper surface outside the groove and the wafer upper surface within the groove that preferably exists.
Polish-induced damage to the alignment mark can be exacerbated by the location of an alignment mark. As stated above, a common location for these marks is near the edge of the wafer. The edge of the wafer is often considered a "no-care" zone of the wafer because of the presence of partial die. Accordingly, device density is often lower near the wafer edge, which may cause different loading effects than in other areas of the wafer. These differences often contribute to making the CMP-induced damage to the wafer surface in and near alignment mark area 104 quite severe.
CMP-induced damage to the alignment mark can cause problems when attempting to properly align an exposure tool relative to the wafer. For example, if the height along the surface of wafer 100 in and near the alignment mark area is significantly distorted from normal, the mark will not reflect light properly and the stepper can receive weak or false signals. Because of such poor signals, the marks in the exposure mask may be translated or rotated from a proper alignment with the marks in wafer 100. The poor feature registration that can result may render the final circuit inoperative.
Therefore, it would be desirable to develop a method for processing a semiconductor substrate that protects an alignment mark formed in the substrate from CMP-induced damage. The alignment mark produced by such a method would thus allow for a greater degree of accuracy and reduced variability when aligning an exposure tool to the substrate.